Abstract: The rapid growth of AI services and large-scale neural networks has made computational efficiency a critical challenge for modern AI hardware. This talk introduces data representation-aware bit-slice architectures as a promising direction for efficient AI acceleration. The proposed approach decomposes data into bit-level or bit-chunk-level representations and exploits the resulting bit sparsity to reduce unnecessary multiply-accumulate operations.  The presentation first reviews the motivation for bit-slice computing and its flexibility in supporting different precision levels. It then explains how data representation can expose redundant or insignificant bit patterns, enabling multiplication skipping and more efficient MAC execution. Building on this idea, the proposed BADA architecture reorganizes bit-slice representation to reduce hardware overhead while preserving numerical correctness.  Evaluation results across representative CNN, Vision Transformer, and language-model workloads show that data representation-aware bit-slice acceleration can provide substantial speedup over conventional approaches and prior bit-slice accelerator designs. This work highlights the importance of co-designing numerical representation, sparsity exploitation, and hardware architecture for next-generation AI accelerators.

Bio: Joon-Sung Yang is a Professor in the Department of System Semiconductor Engineering at Yonsei University, where he has been since 2020. Prior to joining Yonsei, he was on the faculty of Sungkyunkwan University, and before that he worked at Intel Corporation on the Low Power Intel Architecture SoC design team. He began his career at Samsung Electronics in the Flash Memory Design Team. He received his B.S. from Yonsei University and his M.S. and Ph.D. in Electrical and Computer Engineering from the University of Texas at Austin.