Current CPUs are extremely complex with intricate microarchitectural features such as advanced branch predictors. However, understanding the precise impact of these features on performance can be challenging.

To address this problem, we developed a RISC-V Core using Verilog. Our RISC-V Core utilizing an Out-of-Order, 4-stage pipelined architecture will serve as a baseline for our exploration. Then, we would implement various microarchitecture modifications to that Core and graphically represent each microarchitecture modification's performance benefits using metrics such as cycles to run the entire program, maximum clock frequency, etc. 

By systematically evaluating microarchitecture changes and visualizing their performance enhancements, our project aims to provide valuable insights into the optimization of CPU designs for improved efficiency and speed.

Team Members:

Kaeden Cameron

Luke Kaufman

Rathna Sivakumar

Orhan Unuvar

Minho Yoon