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Implementation of a RISC-V ISA on an FPGA

Many students face dilemmas in accessing these tools due to incompatible platforms and operating systems. This project aims to provide a solution to the aforementioned inconsistency by implementing the RISC-V Instruction Set Architecture (ISA) on Field Programmable Gate Arrays (FPGAs) and developing a customizable laptop computer utilizing the RISC-V core, which will be distributed to students. This initiative will provide students with an upgradable foundational tool that resolves compatibility issues between different operating systems, software platforms, and hardware platforms. Furthermore, students will progressively enhance their product as they navigate through the diverse courses in the Electrical and Computer Engineering department.

Team Members:

Amrit Chandar
Chieh-An Chen
Francis King
Jeff Teng
Rongjie Zhao
Xun Zhou
Wenyu Zhu

Semester