Talk Abstract:
With the end of Dennard scaling and the slowing of Moore’s Law, the performance of general-purpose processors has plateaued. At the same time, the energy cost of computing is following a grim exponential trajectory. For these reasons, computing 
systems are widely expected to transition toward highly heterogeneous acceleratorintensive platforms. As system designers prepare for this new era, the focus is largely on designing individual accelerator architectures. Unfortunately, much of the surrounding 
computing stack continues to rely on legacy processor-centric assumptions. This mismatch introduces new headaches when attempting to control, scale, and optimize accelerators in modern heterogeneous systems. In this talk, I will argue that rethinking the rest of the hardware stack around accelerators is key to enable heterogeneity without these headaches. I will first present a processor–accelerator co-design paradigm that enables seamless interleaving between generalpurpose and special-purpose computations. I will then introduce a design that specializes network hardware for distributed sparse applications, enabling sparse accelerators to scale across large clusters. Finally, I will highlight a lightweight machine-learning hardware agent, inspired by slot machines, that can substantially simplify performance optimization across heterogeneous hardware mechanisms. I will conclude by outlining future research directions toward a new generation of accelerator-centric systems capable of sustaining 
scientific and technological progress.

Speaker Bio:
Gerasimos Gerogiannis is a final-year PhD candidate at the University of Illinois at Urbana–
Champaign. His research focuses on computer architecture, with an emphasis on 
heterogeneous computing using accelerators for artificial intelligence and scientific 
applications. His work has appeared in top-tier venues in computer architecture and machine learning, 
including ISCA, MICRO, HPCA, ASPLOS, and ICML. He has filed four U.S. patents with Intel 
on processor–accelerator co-design for machine learning workloads. Among other awards, 
his research has been recognized with one IEEE MICRO Top Pick and one Honorable Mention