Jaydeep Kulkarni, associate professor in the Chandra Family Department of Electrical and Computer Engineering, has been elevated to a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) for 2026 for "for contributions to low-power SRAM and compute-in-memory circuit technologies."
IEEE Fellow is a distinction reserved for select IEEE members whose extraordinary accomplishments in any of the IEEE fields of interest are deemed fitting of this prestigious grade elevation.
The grade of Fellow is conferred upon IEEE Senior Members with outstanding records of accomplishments in any of the IEEE fields of interest. Each year, this honor is limited to no more than 0.1% of the total IEEE voting membership. Fellow is the highest grade of IEEE membership and is recognized as a prestigious honor and an important career achievement.
Texas ECE now has 29 current faculty members who have been elevated to IEEE Fellow.
Jaydeep Kulkarni is an associate professor and holds the Fellow of Silicon Laboratories Endowed Chair in Electrical Engineering in the Chandra Family Department of Electrical and Computer Engineering at The University of Texas at Austin.
He received a B.E. degree from the University of Pune, India, in 2002, an M. Tech degree from the Indian Institute of Science (IISc) in 2004, and a Ph.D. from Purdue University in 2009. From 2009-2017, he worked as a Research Scientist at Intel Circuit Research Lab in Hillsboro, OR. He is an associate professor in the Chandra Department of Electrical and Computer Engineering, a fellow of the Silicon Labs endowed chair in electrical engineering, and the Interim Executive Director of Advanced Packaging Design for Texas Institute for Electronics (TIE) at the University of Texas at Austin.
He has filed 39 patents, published two book chapters, and more than 150 papers in refereed journals and conferences. His research focuses on Integrated circuits and systems, specifically machine-learning hardware accelerators, low-power digital designs, in-memory computing, DTCO/STCO for emerging nanodevices, heterogeneous and 3D integrated circuits, hardware security, cryogenic computing, and superconducting electronics.
He received the Best M. Tech Student award from IISc Bangalore, Intel Foundation Ph.D. fellowship award, Purdue ECE Outstanding Doctoral Dissertation Award, the IEEE Transactions on VLSI Systems Best Paper Award, the SRC Outstanding Industrial Liaison award, Micron Foundation Faculty Awards, Intel Rising Star Faculty Award, NSF CAREER Award, SRC Innovator Award, UT ECE Junior Faculty Excellence in Teaching Award, and IEEE Best Associate Editor Award.
He has served on the technical program committees of the ISSCC, VLSI Symposium, CICC, ASSCC, DAC, ICCAD, ISLPED, AICAS, and VLSI Design conferences. He has been a TPC Co-Chair and General Co-Chair for 2017 and 2018 ISLPED, respectively, and a TPC Co-Chair for the 2023 VLSI Design Conference, India. He has also been an associate editor for IEEE Solid-State Circuits Letters, IEEE Transactions on VLSI Systems, and IEEE Transactions on Circuits and Systems I and II. He has been a distinguished lecturer for the IEEE Electron Device Society, IEEE Circuits and Systems Society and IEEE Solid State Circuits Society. He is a senior member of the ACM and the US National Academy of Inventors.
