As the semiconductor industry approaches the physical limits of Moore's Law, the focus has shifted from transistor scaling to advanced packaging and heterogeneous integration (HI) as key enablers for future high-performance computing (HPC) and medical electronics. While exponential device scaling has driven progress for decades, the slower scaling of package dimensions particularly bump & wiring pitches has become a critical bottleneck, limiting the performance of modern chips due to link latencies & power loss. Conventional packaging, with its coarse interconnects and longer link lengths, relies on energy-hungry SerDes for high-data-rate communication, leading to significant power losses and latency. Advanced packaging, with fine-pitch, high-density interconnects, offers a solution by enabling efficient, high-bandwidth parallel communication between compute and memory chips, which is essential for next-generation HPC systems. Similarly, medical electronics demand highly complex systems with heterogeneous integration of multiple components, operating at low power and within small form factors. Advanced packaging and HI are critical to meeting these challenging requirements as they allow the use of non-conventional substrates with seamless integration of heterogenous materials and devices at high densities with fine pitch wiring in compact form factors. Designing such densely packaged heterogeneous systems presents unique challenges: efficient and universal chip-to-chip and system-to-system communication, high-density power delivery, thermal management, and chip-package interactions requiring Multiphysics simulations for reliable design. Addressing these challenges opens opportunities for novel interdisciplinary solutions that will be explored in this talk.
Biography:
Currently, I am an R&D engineer in advanced packaging and serving as the Deputy Director of UCLA CHIPS. I oversee daily operations and provide guidance to PhD and master's students on their research projects. In addition to my administrative role, I conduct independent research (as a research engineer) in RF packaging and photonics, focusing on high-speed connectors exceeding 200 Tbps for the silicon interconnect fabric (Si-IF). I am also working on a project that uses a magnetic transformer based backside power delivery for wafer scale systems.
From Jan 2023-Sept 2024, I worked as a senior project associate in CPPICS Lab, IIT-Madras on the topic of Optical Packaging and high speed RF design for photonics. The research was experimental in nature and focused on design and fabrication of optical packages for Si-Photonic Integrated Circuits (PICs) with the development of optical fiber-array attach schemes for the same. The project also involved the design and fabrication of high speed RF PCBs (>50GHz) to enable RF data transmission to the PIC. Typical target applications for the integrated photonic systems are in quantum communication for Quantum Key Distribution (QKD) as well as for microwave photonics.
From Jun 2017-Dec 2021, I was a Graduate Research Assistant at the Center for Heterogeneous Integration and Performance Scaling (CHIPS), UCLA. For my thesis topic, I worked on GaN microLED mass transfer and assembly on flexible organic substrates using Fan-Out Wafer-Level Packaging (FOWLP) for wearable Augmented Reality (AR) and biomedical applications. I have two patents in this technology, one on flexible display arrays (published) and another on large area microLED testing (pending).
Overall, I have a broad range of expertise in advanced packaging, heterogeneous
integration, semiconductor process development, display technology, optical packaging and Integrated Si-photonics.
