As the semiconductor industry approaches the physical limits of Moore's Law, the focus has shifted from transistor scaling to advanced packaging and heterogeneous integration (HI) as key enablers for future high-performance computing (HPC). While exponential device scaling has driven progress for decades, the slower scaling of package dimensions particularly bump & wiring pitches has become a critical bottleneck, limiting the performance of modern chips due to link latencies & power loss. Conventional packaging, with its coarse interconnects and longer link lengths, relies on energy-hungry SerDes for high-data-rate communication, leading to significant power losses and latency. Fan-Out Wafer-Level Packaging (FOWLP), with fine-pitch, high-density interconnects, and embedded bare-die components without the use of solder offers a potential solution. FOWLP enables seamless integration of heterogeneous components like compute and memory chips with high BW-density interconnection. Conventional FOWLP like TSMC’s InFO has however struggled to push the wiring pitches to less than 10 microns due to issues like die-shift and warpage. At UCLA, we have developed a novel FOWLP process called FlexTrateTM that uses PDMS as the substrate. The unique mechanical properties of viscoelastic PDMS along with novel adaptive lithographic techniques allows us to minimize die-shifts & warpage effects and push the wiring pitches to < 2 microns. In this talk, I will discuss the FlexTrateTM process, challenges for future development and its potential for packaging future HPC systems.

Biography

Goutham Ezhilarasu is an R&D Engineer in Advanced Packaging and Deputy Director of UCLA CHIPS, where he leads daily operations and mentors graduate students in packaging research. His current work focuses on high-speed flexile connectors (>200 Tbps) for silicon interconnect fabric (Si-IF) and backside power delivery for wafer-scale systems. Previously, at IIT-Madras, he designed >50 GHz RF PCBs and developed optical fiber-array attach schemes for silicon photonic integrated circuits (PICs), advancing quantum communication (QKD) and microwave photonics. He is a recipient of two patents for innovations in flexible microLED arrays and large area microLED testing methodologies, developed during his graduate research at UCLA. His PhD thesis on GaN microLED assembly via Fan-Out Wafer-Level Packaging (FOWLP) pioneered flexible AR and biomedical display technologies. He holds bachelor’s degree in electrical and Electronics Engineering from CEG, Anna University, India.