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Improving Integrated Circuits

Professor David Pan and UT graduate students, Ashutosh Chakraborty and Anurag Kumar, took home the $25,000 Grand Prize in the eASIC Placement Design Challenge. The worldwide competition was to create a tool that determines the most efficient placement of components on a structured application-specific integrated circuit (ASIC) platform. Placement with shorter wirelength translates to better performance and less power consumption. Their placement tool, RegPlace, outperformed the second place team from the University of Michigan by 15% in total wirelength.

Pan, Chakraborty, and Kumar are members of the UT Design Automation Lab (UTDA). RegPlace will be made available open source to the public for further research and development.