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Prof. David Pan and Students Win IBM Research 2010 Pat Goldberg Memorial Best Paper Award

UT ECE professor David Pan and students have received the IBM Research 2010 Pat Goldberg Memorial Best Paper Award. This award is selected among all published papers in CS, EE, and Math, (co-)authored by IBM researchers in 2010. Close to 120 papers in computer science, electrical engineering and mathematical sciences published in refereed conference proceedings and journals in 2010 were submitted by IBM Research authors worldwide for the 2010 Pat Goldberg Memorial Best Paper Awards in CS, EE and Math. From these submissions, the IBM Research Professional Interest Communities (PICs) nominated 34 papers based on technical significance (depth and breadth) and expected impact on computer science, electrical engineering or mathematical sciences, or their applications in the research disciplines covered by the PICs. A committee consisting of the PIC site coordinators and head of IBM Computer Science Laura Haas reviewed the nominated papers and selected four winners of the 2010 Pat Goldberg Memorial Best Paper Awards.

The winning paper by Prof. Pan and his (former) students is “A New Graph Theoretic, Multi-Objective Layout Decomposition Framework for Double Patterning Lithography.” Along with Prof. Pan, co-authors include Jae-Seok Yang (UT Austin), Katrina Lu (Intel), Minsik Cho (IBM T. J. Watson Research Center), and Kun Yuan (UT Austin).The paper was presented at the Asian and South Pacific Design Automation Conference (ASPDAC 2010).

Double patterning lithography (DPL) is the leading photolithography technology candidate for 14nm, and may be further extended as triple/quadruple patterning for sub-7nm nodes. Layout decomposition is a fundamental step in DPL which splits the original layout into two orthogonal sub-masks (resulting in litho-etch-litho-etch process). It has several key challenges: a) each sub mask has to be conflict-free, i.e. satisfying all DPL rules as well as the design rules, b) the stitch count (which is created when a single polygon is severed) should be minimized for higher tolerance against significant overlay errors (e.g., 3?=5nm), and c) each sub mask should have similar pattern density for better lithographic results.

In this paper, the authors first proved that layout decomposition for DPL is equivalent to a well-researched constrained min-cut graph partitioning problem (solving challenges a and b). And then, the authors proposed a new partitioning framework to address other DPL challenges (challenge c) based on the overlay self-compensation concept and balanced partitioning objective, which is to enhance overall manufacturing yield. Compared with previous state-of-the-art works which relied on integer linear programming, the proposed algorithm is order-of magnitudes faster and provides near-optimal decomposition results, yet considers multi-objective functions seamlessly which none of the previous work could. For example, the proposed approach achieved over a 10^5 speedup with 0.5% quality degradation for the largest circuit the previous work could handle.

Given that DPL's importance in the sub-14nm manufacturing in the semiconductor industry, the paper received the Best Paper Award at ASPDAC 2010, an IBM PIC targeted conference, due to both theoretical elegancy and significant real-world impact.

Dr. David Z. Pan is an Associate Professor in the Department of Electrical & Computer Engineering at The University of Texas at Austin. He received his Ph.D. degree (with honor) in Computer Science from University of California at Los Angeles (UCLA) in 2000. From 2000 to 2003, he was a Research Staff Member with the IBM T. J. Watson Research Center, Yorktown Heights, NY. He has published over 150 technical papers in refereed journals and conferences, and is the holder of 8 U.S. patents. His research is mainly focused on nanometer design for manufacturing/reliability, intersection of physical and system-level co-design, and CAD for emerging technologies.

Dr. Minsik Cho, a former PhD student of Prof. Pan, has been with IBM T. J. Watson Research Center since 2008 as a Research Staff Member in VLSI Design Automation Department.